Every line of Python you write eventually becomes a sequence of instructions executed by a processor. This section covers the architecture that makes that happen: the CPU, memory, buses, and the fetch-decode-execute cycle.
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EveryoneThis section is foundational for the entire A Level. The architecture topics appear in Unit 1 (written paper) and connect directly to assembly language, operating systems, and performance topics later in the course.
Von Neumann architecture
Almost every general-purpose computer ever built follows the same fundamental design, proposed by John von Neumann in 1945. The key idea is simple but powerful: store both the program and the data it operates on in the same memory. Before this, programs were often hardwired into the machine.
A Von Neumann machine has four main components:
The three buses are the communication channels between components. Each carries a different kind of signal:
Bus
Direction
Purpose
Address
CPU to memory
Carries the memory address the CPU wants to read from or write to. One-way only.
Data
Both directions
Carries the actual data or instruction being transferred between CPU and memory.
Control
Both directions
Carries control signals: read/write signals, clock pulses, interrupt requests.
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New to CSThink of the address bus as a postal address written on an envelope, the data bus as the contents inside, and the control bus as the postal service instructions (send, receive, priority). You cannot have data without knowing where it came from or where it is going.
Registers
Registers are tiny, extremely fast storage locations inside the CPU itself. They hold the data the CPU is working on right now. There are only a small number of them, but accessing a register is orders of magnitude faster than accessing main memory.
Four registers are essential for the fetch-decode-execute cycle:
Register
Full name
What it holds
PC
Program Counter
The memory address of the next instruction to be fetched. Increments automatically after each fetch.
MAR
Memory Address Register
The address in memory that the CPU currently wants to read from or write to. Connected directly to the address bus.
MDR
Memory Data Register
The data that has just been read from memory, or the data about to be written to it. Connected directly to the data bus. Also called MBR (Memory Buffer Register).
ACC
Accumulator
Stores the result of the most recent arithmetic or logic operation performed by the ALU.
CIR
Current Instruction Register
Holds the instruction currently being decoded and executed.
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ExtensionModern processors have many more registers than this: modern x86-64 chips have 16 general-purpose registers (RAX, RBX, RCX...) plus specialised registers for floating-point, SIMD operations, and system state. The ones above are the ones the A Level focuses on. If you are curious, look up "x86 register reference" and you will see how much further it goes.
The fetch-decode-execute cycle
The CPU does not understand programs. It understands one thing: fetch an instruction from memory, decode what it means, execute it, then repeat. Billions of times per second. This is the fetch-decode-execute cycle, sometimes called the instruction cycle.
Fetch 1/3
Copy the program counter to the MAR
The PC holds the address of the next instruction. This address is copied to the MAR, which places it on the address bus so memory knows where to look.
Fetch 2/3
Read the instruction from memory into the MDR
Memory sends the instruction at the address in the MAR across the data bus into the MDR. The PC is simultaneously incremented to point at the next instruction.
Fetch 3/3
Copy the instruction from the MDR into the CIR
The instruction in the MDR is copied to the CIR. The MDR is now free to be used for any data reads or writes the execution step may need.
Decode
The Control Unit decodes the instruction in the CIR
The Control Unit reads the instruction in the CIR and determines what operation is required, what data (operands) it needs, and which part of the CPU or memory is involved.
Execute
The instruction is carried out
Depending on the instruction type: the ALU performs a calculation and stores the result in the ACC; or data is moved between registers and memory; or the PC is changed (for a jump or branch). The cycle then repeats.
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New to CSWhen you write x = 5 + 3 in Python, the Python interpreter eventually breaks that down into a sequence of instructions like: load the value 5 into a register, load the value 3, add them using the ALU, store the result. What looks like one line of code to you is several FDE cycles at the hardware level.
The memory hierarchy
Not all memory is equal. There is a fundamental tradeoff in computer design: faster memory costs more and cannot be made as large. Slower memory is cheaper and can be made much larger. Computer architects solve this with a hierarchy: small amounts of very fast memory close to the CPU, backed by increasingly large but slower storage further away.
Fastest Smallest Most expensive
Registers ~1 ns
Bytes Inside CPU
Cache (L1/L2/L3) ~5 ns
KB to MB On/near CPU chip
Main memory (RAM) ~100 ns
GB Motherboard
SSD storage ~100 µs
TB Internal drive
Slowest Largest Cheapest
HDD / optical / cloud ~10 ms+
TB+ Internal/external
The numbers matter: a register access takes around 1 nanosecond. A hard drive access takes around 10 milliseconds. That is a factor of 10 million. A program that constantly reads from disk instead of keeping data in RAM will run millions of times slower than one that uses memory efficiently. This is why understanding the hierarchy matters for writing performant software.
Cache memory
Cache sits between the registers and main memory. When the CPU needs data, it first checks the cache. If the data is there (a cache hit), it can be retrieved in nanoseconds. If not (a cache miss), the CPU fetches the data from RAM and stores a copy in cache, anticipating that it might be needed again soon.
Modern CPUs have multiple cache levels: L1 (smallest, fastest, one per core), L2 (larger, slightly slower), and L3 (shared across cores, largest and slowest of the cache levels). You will study cache replacement policies and the principle of locality at A Level.
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ExtensionThe Von Neumann bottleneck refers to the limited bandwidth between CPU and memory: the processor can compute far faster than it can move data to and from RAM. Cache is one solution. Other approaches include pipelining (starting the next FDE cycle before the current one finishes), branch prediction, and out-of-order execution. These are fascinating topics and all are on the A Level specification.
Why this connects to your code
When Python runs a program, it does not run directly on the hardware. The Python interpreter reads your code, compiles it to an intermediate bytecode, and executes that bytecode. But underneath every operation you write, the hardware is cycling through fetch-decode-execute instructions, moving values through registers, and reading and writing memory.
Understanding the architecture helps you reason about performance. A loop that repeatedly accesses a large array may cause many cache misses. Recursion that goes very deep fills up the call stack in RAM. A program with a memory leak gradually consumes all available RAM until the operating system intervenes.
You do not need to think about this every time you write Python. But when something is slow, or crashes with a memory error, the hardware model is where the explanation lives.
Practice questions
Try each question before revealing the answer.
Q1What is the key characteristic of Von Neumann architecture that distinguishes it from earlier computers?
Programs and data are stored together in the same memory.
Earlier machines had hardwired programs. Storing programs as data meant a single machine could run any program by loading it into memory.
Q2What does the Program Counter hold, and what happens to it during the fetch stage?
The address of the next instruction to be fetched.
During the fetch stage, the PC is copied to the MAR, and then the PC is incremented so it points at the instruction after the one currently being fetched.
Q3What is the difference between the MAR and the MDR?
MAR holds an address. MDR holds data (or an instruction).
The MAR is connected to the address bus and tells memory where to look. The MDR is connected to the data bus and receives what comes back.
Q4Put these memory types in order from fastest to slowest: RAM, L2 cache, hard disk drive, registers.
Registers → L2 cache → RAM → HDD
Registers (~1 ns), L2 cache (~5-10 ns), RAM (~100 ns), HDD (~10 ms). Each step down is roughly 10-100x slower.
Q5Explain what a cache miss is and what happens when one occurs.
The CPU needs data that is not currently in cache.
When a cache miss occurs, the CPU must fetch the data from the slower main memory (RAM). A copy is then stored in cache so future accesses to the same data can be served from cache instead.
Q6Which bus is unidirectional (one-way only), and why does that make sense?
The address bus. It only ever carries addresses from the CPU to memory.
Memory never needs to tell the CPU an address. The CPU always initiates the request. Data and control signals, by contrast, can flow in either direction depending on whether the CPU is reading or writing.